• ChipQuake^TM provides fast frequency domain simulations of noise coupling in mixed signal integrated circuits, including the effects of package and printed circuit boards (PCBs). 
• ChipQuake^TM allows design engineers and system architects to visualize noise coupling tradeoffs at the architectural stages of the design process.
• ChipQuake^TM simulations in early stages enable better decisions regarding chip architecture, package and PCB definition, fabrication technology options, and power distribution design.

Overview:

     The effects of noise coupling are often noticed after fabrication, during characterization, or even after shipment to customers. Because of this, a large effort has been made in recent years to develop modeling techniques that predict the noise coupling before fabrication. 

     The prediction accuracy depends on the level of detail in the circuit description, which is imprecise in early architectural stages of designs and gradually increases in complexity as projects advance through the design process. The modeling techniques based on the physical layout are more accurate than the modeling techniques using the schematic, or architectural definition.
     However, the dominant noise coupling issues are related to the floor plan, pins assignment, guard rings, and the overall power distribution. Problems found in these areas often require major changes if discovered right before tape-out or even before layout. 

     Therefore, especially in large and complex integrated circuits, it is essential to identify potential noise coupling issues early in the architectural definition of the project. ChipQuake^TM tries to solve this problem by providing a solution for noise coupling simulation in early stages of the design flow.

ChipQuake^TM Can Be Used To:

Evaluate the noise coupling effects on the analog regions of mixed-signal integrated circuits.

Study the feasibility of implementing the entire functionality on a single chip (SOC) or to split it on multiple chips (MCM, SIP).

Examine various floor-plan options, pin assignments, power grid sizes, and guard ring isolations.

Analyze the effects of various packaging options on noise coupling.

Explore decoupling capacitor types, values, and placement locations on the chip, package, and PCB.

Identify potential noise coupling issues early in the design flow, thus preventing the cost and schedule impact caused by finding noise coupling problems close to tape-out.

Perform what-if architectural experiments to improve the performance and reduce cost.

Inputs:

ChipQuake^TM uses the information available in the design specifications, technology manual, package datasheet or specifications, and statistical data from typical design practices or previous designs.

Outputs:

ChipQuake^TM generates two- and three-dimensional color coded maps of the substrate and power supply noise. Mouse move probing displays the noise voltage function of X-Y coordinates. ChipQuake^TM generates also the frequency characteristics of noise coupling at any X-Y coordinate in the analog region.

Simulation Time:

ChipQuake^TM is a fast simulator. Most simulations take only a few minutes.

Accuracy:

The estimation accuracy is lower compared to that provided by post- and pre-layout extraction and simulation tools but good enough to identify major noise coupling issues in early stages of the design flow.

Download ChipQuake Datasheet (PDF)

Download ChipQuake User Guide (PDF)