Coverage:

• Noise Coupling
• Power Integrity
• Signal Integrity

Technologies:

• Chip: CMOS, BiCMOS, GaAs, InP, Bipolar, Lightly and heavily doped substrates, SOI, SoC
• Package: SIP, MCM, BGA, Flip-Chip, Lead-Frame, Stacked Dies, and any novel technology 

For New Products:

• Modeling and simulation of noise coupling and power integrity in the whole chip-package-PCB co-design (post-layout, pre-layout, and architectural exploration)
• Implementation of efficient suppression techniques that address the noise coupling mechanisms in your specific chip-package-PCB co-design
• Independent design review in architectural stage of the design, pre-layout, and post-layout
• Identify noise coupling and signal integrity problems, ground loops, electric and magnetic shields, system level voltage and current reference distribution, power and ground distribution architecture, mixed-signal interference, signal crosstalk, and noise filtering
• Implement noise coupling measurement structures

For Existing Products:

• Noise coupling and power integrity failure analysis, troubleshooting, and problem solving
• Signal integrity troubleshooting and problem solving: chip, package, PCB, wires, and interconnects
• Identify the sources of various types of timing jitter on waveforms and develop solutions
• Develop solutions for improving waveform degradation: overshoot, undershoot, multiple reflections, inter-symbol interference
• Troubleshoot ground loops and shielding problems
• Modeling of functionality and performance issues, correlation with measurements, and solutions validation on the correlated models

 Consulting and Team Mentoring Prices