Consulting Services
Chip, Package, PCB, System Level
Noise Coupling
Power Integrity
Signal Integrity
Technologies: CMOS, BiCMOS, GaAs, InP, Bipolar, lightly and heavily doped substrates, SOI, SoC, SIP, MCM, BGA, Flip-Chip, Lead-Frame, Stacked Dies, and any novel or experimental technology
For New Products:
Modeling and simulation of noise coupling and power integrity in the whole chip-package-PCB co-design (post-layout, pre-layout, and architectural exploration)
Implementation of efficient suppression techniques that address the specific noise coupling mechanisms in your chip-package-PCB co-design
Independent design review: architecture, schematics, and layout of chips, packages, PCBs, high-speed interconnects, and systems
Second opinion analysis on design strategies for reducing noise coupling effects and improving the signal and power integrity
For Existing Products:
Noise coupling and power integrity failure analysis, modeling, troubleshooting, and problem solving
Signal integrity troubleshooting and problem solving: chip, package, PCB, and interconnects
Power integrity and noise coupling effects on signal integrity; identification of deterministic jitter components and their source in your chip/package/PCB co-design.
All consulting services are performed by Dr. Cosmin Iorga, who brings 20+ years of experience in circuit design and troubleshooting at chip, board, and system levels. (read short bio in "AboutUs")
Free Q&A Service
Have a technical question or problem on noise coupling or signal integrity? Try for free: "Ask Cosmin"
Dr. Cosmin Iorga will send you a response to your question at the provided contact information.