Course Title: Power Integrity and Noise Coupling in Chip-Package-PCB Co-Design
Instructor: Dr. Cosmin Iorga
Duration: 8-hours
Course Major Topics:
Power distribution networks on the chip/package/PCB co-design, power distribution impedance and resonance peaks, noise generation on power supplies and in the chip substrate, noise propagation in lightly doped, heavily doped, and silicon-on-insulator (SOI) substrates, noise coupling effects on devices and circuits, modeling and simulation of noise coupling in power distribution and substrate, suppression techniques for noise generation, propagation, and reception.
Course Syllabus:
This course is intended for working engineers and professionals. The main focus is to build a strong understanding of the physical principles that describe the noise coupling and power integrity in integrated circuits and to develop the analysis skills needed by engineers to create robust designs and efficient solutions to complex problems in their daily work.
Topics include power distribution impedance in chip/package/PCB co-design, loop inductance, effective decoupling techniques, power distribution impedance variation with frequency and resonance peaks, noise generation in the substrate and power distribution network, noise propagation in various types of substrates and fabrication technologies, noise reception in sensitive circuits, noise coupling suppression techniques, and noise coupling modeling and simulation.
The learning approach balances qualitative and quantitative analysis methods with practical intuitive techniques for understanding the physical phenomena. Along this course you will be exposed to various practical examples and are guided to complete a design project in which they develop the power distribution network and simulate the noise coupling effects in a mixed-signal integrated circuit.
Course Materials (included in the registration):
Course Textbook:
“Noise Coupling in Integrated Circuits: A Practical Approach to Analysis, Modeling, and Suppression”, Cosmin Iorga, 2008, ISBN: 978-0-615-19756-2
Simulation Software Tool:
ChipQuakeTM Power Integrity Explorer Learning Edition
Course Goals and Objectives:
After completing this course, attendees are expected to be able to analyze various aspects of noise coupling and power integrity in integrated circuits, identify the root cause of problems, and provide highly innovative and efficient solutions. Designers are expected to be able to develop efficient power distribution networks, select the right decoupling capacitors, choose and implement the right noise coupling suppression techniques that match the corresponding noise coupling mechanisms in their specific applications, and choose the right set of simulation tools that cover all the existing power distribution and noise coupling mechanisms in their chip/package/PCB co-design. System architects are expected to be able to identify power integrity and noise coupling problems early in the design process and come up with solutions and guidelines for reducing the noise generation in digital circuits, suppressing the noise propagation, and minimizing the noise injection into sensitive circuits.
Course Program:
Morning session: Lecture and Question & Answers Session (about 4-hours)
Fundamental Concepts
Power Distribution Networks
Noise Generation Mechanisms
Noise Propagation and Reception
Suppression Techniques
Modeling and Simulation
Afternoon session: Course Project Work - Design the power distribution network to and integrated circuit mounted on a flip-chip BGA package and on a printed circuit board (PCB)
Project Overview
In this project you are part of an architectural exploration team for a sub-system board consisting of an integrated circuit mounted on a printed circuit board. The integrated circuit is manufactured in flip-chip technology and it is mounted on a Ball-Grid-Array (BGA) package. Further more, this integrated circuit contains a digital core, operating at 500 MHz clock frequency, and an analog block. Your task is to evaluate the power distribution network (PDN) in the overall chip/package/PCB sub-system. Part of this work you will estimate the frequency characteristics of the power distribution impedance as seen by the digital core, you will analyze the power distribution decoupling function and will recommend a set of capacitors that will reduce the PDN impedance, you will estimate the power distribution and substrate noise in the analog block, and you will make recommendations for the floorplan location of a voltage controlled oscillator (VCO) in this analog block. This VCO is a critical performance part of a phase-locked-loop (PLL) circuit and it is very sensitive to substrate and power supply noise, so you will choose a location that would minimize this noise.
Part A: Calculations
Calculation of power distribution inductance in a chip-package-PCB design:
Part B: Modeling and Simulation
Building a model of the power distribution network and simulating using ChipQuake Power Integrity Explorer software:
Part C: Decoupling Capacitors Optimization
Optimize the values and types of decoupling capacitors on the package and PCB to achieve a low impedance of the power distribution network over the functionality spectral frequency range.
Each participant receives a copy of the textbook and ChipQuake Simulation Software Learning Edition.
Instructor Biography
Dr. Cosmin Iorga
Dr. Cosmin Iorga is the founder of NoiseCoupling.com. He has earned his Ph.D. in electrical engineering from Stanford University. Cosmin has accumulated over 20 years of experience in high-speed analog circuit design and troubleshooting at system, board, and integrated circuit levels, with emphasis on signal integrity and noise coupling reduction. Cosmin has filed more than 15 patents with 9 granted so far, covering innovative solutions in noise coupling reduction and signal integrity. Cosmin is the author of the book “Noise Coupling in Integrated Circuits: A Practical Approach to Analysis, Modeling, and Suppression”. Dr. Cosmin Iorga teaches all the technical courses and team mentoring offered by NoiseCoupling.com.